1. Field of the Invention
The present invention relates to an organic electroluminescent display, and in particular, to an organic electroluminescent display that prevents pad electrodes from being over-etched by removing the thickness difference of a passivation layer including via holes between an array portion and a pad portion.
2. Description of Related Art
Generally, an electroluminescent (EL) display is a display device that utilizes the principle that electrons from a cathode and holes from an anode are injected into a light emission layer while being combined to form excitons, and the light emission layer emits light when the excitons go down from the excited state to the ground state.
In contrast to a conventional thin film transistor liquid crystal display, an organic EL display does not need a separate light source and uses a lightweight structure having a reduced volume. In an organic EL display, organic material films, which emit light under the application of electric current, are arranged at respective pixels in a matrix form, and the amount of electric current applied to the organic material films is varied to display desired images. The organic EL display has numerous advantages, such as low-driving voltage, lightweight, flatness, wide viewing angle, and fast response time. Furthermore, organic EL displays are expected to be a next-generation display device.
The organic EL display includes a plurality of pixels arranged in a matrix form, and many thin film patterns formed at each pixel region, such as a thin film transistor for a switching and driving element, a pixel electrode, and an organic EL film.
Referring to the drawings, FIG. 1 is a cross-sectional view of an organic EL display 15 configured in accordance with the prior art. As shown in FIG. 1, the organic EL display 15 has a panel with an array portion A for forming pixels, and a circuit pad portion P placed at the periphery thereof to be connected to an external power supply (not shown). A blocking layer 2 made of SiO2 is formed on an insulating substrate layer 1, and a polycrystalline silicon layer 3 is formed on the blocking layer 2 having a predetermined width.
Source and drain regions 3c and 3a, respectively, doped with a high concentration of impurities are formed at the polycrystalline silicon layer 3, and a channel region 3b is formed between the source region 3c and the drain region 3a.
A gate insulating layer 4 of SiO2 or Si3N4 is formed over the entire surfaces of the blocking layer 2 and the polycrystalline silicon layer 3. Gate electrodes 5a and 5b made of Al are formed on the gate insulating layer 4 having a predetermined width, and an inter-layered insulating layer 6 is formed on the gate insulating layer 4 and the gate electrodes 5a and 5b. 
Source electrode 7a and drain electrode 7b, respectively, made of Al are formed on the inter-layered insulating layer 6 so that the source electrode 7a and the drain electrode 7b are connected to the source region 3c and the drain region 3a, respectively. First and second insulating passivation layers 8 and 9, respectively, are formed on the source electrode 7a and the drain electrode 7b, forming a flat top surface thereof.
The first and second insulating passivation layers 8 and 9, respectively, are selectively etched such that they expose the source electrode 7a and the drain electrode 7b. A conductive layer 10 fills the etched portion of the first insulating passivation layer 8 and the second insulating passivation layer 9 and a pixel defining layer 11 is formed on the conductive layer 10. The pixel defining layer 11 is selectively etched to form pixel regions 12.
During the process of forming the first insulating and second insulating passivation layers 8, 9, the first insulating passivation layer 8 having a thin thickness is first formed, and the second insulating passivation layer 9 having a thick thickness is then formed thereon having a flat top surface to make a uniform topology. The first insulating passivation layer 8 exhibits the topology of the underlying structure as it is formed on that structure with a uniform thickness, similar to the insulating substrate layer 1. The second insulating passivation layer 9 removes the surface stepped differences in the underlying structure and forms a flat top surface over the entire area of the wafer.
The first and second insulating passivation layers 8, 9 must have a flat top surface over the entire area of the insulating substrate 1 in order to conduct a photolithography process for forming via holes 20 subsequently. The via holes 20 exposing the source and drain electrodes 7a and 7b, respectively, are formed after the formation of the first and second insulating passivation layers 8, 9. By means of the via holes 20, metallic element or conductive layer 10 at the array portion A is connected to the underlying drain electrode 7b, while the pad electrode 19 at the pad portion P is connected to the underlying pad 7c.
However, the first and second insulating passivation layers 8, 9 have different thickness depending upon the surface step differences of the underlying structure. More specifically, the source and drain electrodes 7a, 7b alone, or the source and drain electrodes 7a, 7b plus the gate electrode 5b, or the source and drain electrodes 7a, 7b plus the gate electrodes 5a, 5b plus the polycrystalline silicon layer 3 may be under the first and second insulating passivation layers 8,9.
The difference in thicknesses of the first and second insulating passivation layers 8, 9 is formed between the array portion A and the pad portion P. Due to the thickness difference of the first and second insulating passivation layers 8, 9, the etching depth for forming the via holes 20 is different between the array portion A and the pad portion P.
As shown in FIG. 1, the thickness of the second insulating passivation layer 9 to be etched at the pad portion P is indicated by T1, and the thickness of the second insulating passivation layer 9 to be etched at the array portion A is indicated by T2. T1 is clearly shown as being smaller than T2. Except for the first insulating passivation layer 8 which has a uniform thickness, the etching depth for forming the via holes 20 is different between the array portion A and the pad portion P by the value of T2 subtracted by T1.
As the difference in the etching depth for forming the via holes 20 becomes greater, the thicker portions of the first and second insulating passivation layers 8,9 at the array portion A are etched until the underlying source and drain electrodes 7a, 7b are exposed, while the thinner portions of the first and second insulating passivation layers 8,9 at the pad portion P, as well as the underlying pad 7c, are etched continuously. This results in over-etching of the pad 7c.
The over-etching of the pad 7c at the pad portion P becomes more severe when the difference in the etching depth of the first and second insulating passivation layers 8, 9 for forming the via holes is 3000Å or more. Then electrode over-etching causes contact failures.
Accordingly, there is a need to prevent pad electrodes from being over-etched during the via hole formation process due to differences in thickness of the passivation layer.